A review paper on memory fault models and test algorithms

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist the memory are described, terms of definition detection requirement. Several testing algorithms that used built-in self-test (BIST) discussed, test operation sequences, ability, also complexity. From studies, it shows tests with 22 N complexity such as March SS AB needed detect all static unlinked or simple faults within cells. The algorithm refers Nx*Ny*Nz whereby Nx represents number rows, Ny columns Nz banks. This paper looks into optimization further improvement achieved on existing increase coverage reduce